1. Field of the Invention
The present invention relates, generally, to a printed circuit board (PCB) including embedded chips, and a fabricating method thereof. More particularly, the present invention relates to a PCB including embedded chips, which comprises a central layer having an embedded chip, an insulating layer formed on one surface or both surfaces of the central layer and having a through hole filled with conductive ink, and a circuit layer formed on the insulating layer and having a via hole and a circuit pattern electrically connected to the chip of the central layer through the through hole of the insulating layer, and a method of fabricating such a PCB. The method of fabricating the PCB according to the present invention includes forming a circuit layer having a predetermined circuit pattern, vertically forming a via hole through a base substrate having a cured resin layer and a non-cured resin layer, filling the via hole with conductive ink, instead of a plating process, superimposing a passive component or an active component on the base substrate, and heating and compressing the circuit layers and the insulating layers on the base substrate at one time, to manufacture a multi-layered PCB.
2. Description of the Related Art
With the great improvement of electronic industries, to correspond to electronic products requiring miniaturization and high functionality, electronic technologies have been developed to insert resistors, capacitors, ICs (integrated circuits), etc., into substrates.
Although discrete chip resistors or discrete chip capacitors have long since been mounted on PCBs, PCBs including embedded chips, such as resistors or capacitors, have only recently been developed.
In techniques of manufacturing PCBs including embedded chips, the chips, such as resistors or capacitors, are inserted into an outer layer or an inner layer of the substrate using novel materials and processes, to substitute for conventional chip resistors and chip capacitors.
That is, the PCB including embedded chips means that the chips, for example, capacitors, are embedded in the inner layer of the substrate itself or outer layer thereof. Regardless of the size of the substrate itself, if the chip is incorporated into the PCB, this is called an ‘embedded chip’. Such a substrate is referred to as an ‘embedded chip PCB’.
The major characteristic of the embedded chip PCB is that the chip is intrinsically provided in the PCB without the need to mount the chip on the substrate.
In general, fabrication techniques of the embedded chip PCB are largely classified into three types.
First, a method of manufacturing a polymer thick film type capacitor is provided, including applying a polymer capacitor paste, which is then heat cured, that is, dried. Specifically, this method includes applying a polymer capacitor paste onto an inner layer of a PCB, and drying the polymer capacitor paste, on which a copper paste is then printed and dried, to form electrodes, thereby obtaining an embedded capacitor.
Second, a method of manufacturing an embedded discrete type capacitor is provided, including coating a PCB with a ceramic filled photosensitive resin, which has been patented by Motorola Co. Ltd., USA (U.S. Pat. No. 6,606,793). The above method includes applying the photosensitive resin containing ceramic powder on the substrate, laminating a copper foil layer on the resin layer to form upper electrodes and lower electrodes, forming a circuit pattern, and then etching the photosensitive resin, thereby obtaining a discrete capacitor.
Third, a method of manufacturing an embedded capacitor is provided, including separately inserting a dielectric layer having capacitance properties into an inner layer of a PCB, so as to substitute for a decoupling capacitor mounted on a PCB, which has been patented by Zycon Corp. Ltd., USA (U.S. Pat. No. 5,079,069). In this method, the dielectric layer having power electrodes and ground electrodes is inserted into the inner layer of the PCB, thereby obtaining a power distributed decoupling capacitor.
To fulfill various functions and superb performance of electronic products, higher speed electronic components are increasingly required. Also, with the aim of increasing the speed of the component, a package bonding manner is changed from typical bonding manners, such as lead frame, wire bonding, pin type bonding, etc., into a small ball type bonding manner or a flip-chip bonding manner.
In the case of a high speed product that adopts a flip-chip bonding manner or in the case of a central processing unit (CPU) or a graphic chip set, a clock is operated at a speed of 2 GHz or more.
Such a CPU or chip set requires a short signal rising time and a high current, and is designed to further decrease intervals between signal lines of an IC, flip chip package and a main board for operation at high speeds.
However, as the speed of the component increases, voltage fluctuation of a power line occurs, resulting in the generation of a lot of high frequency noise, such as SSN (Simultaneous Switching Noise) or delta-I (ΔI).
The high frequency noise (e.g., SSN) causes system delay or a logic fault, thereby decreasing the performance and reliability of the system.
Therefore, the SSN may be effectively reduced by lowering the inductance of the power line when the current and the switching speed required for the operation of devices are unchangeable. In addition, the decoupling capacitor is used to reduce the voltage fluctuation of the power line.
The decoupling chip capacitor is mounted to the power line, whereby a current required for switching the circuit can be directly fed. Thus, the inductance of the power line is shielded, and hence, a voltage drop phenomenon is remarkably lowered and the SSN may be reduced, too.
FIGS. 1a to 1f sequentially show a process of fabricating a PCB including embedded chips, according to a first conventional technique, which is disclosed in Japanese Patent Laid-open Publication No. 2004-7006.
In FIG. 1a, an insulating layer 1 is processed to have a hollow portion 3 therethrough, and also, through holes 2 are formed through the insulating layer 1 and filled with conductive ink.
In FIG. 1b, a circuit forming process is performed on a protective film 6, and thus, a predetermined circuit pattern 4 is formed thereon.
In FIG. 1c, an electrical component 5 is mounted on the circuit pattern 4.
In FIG. 1d, the insulating layer 1 having the through holes 2 filled with the conductive ink adheres to the circuit pattern 4.
In FIG. 1e, the protective film 6 is removed from the circuit pattern 4, to form a central layer 1.
In FIG. 1f, circuit layers 7 and 8 having predetermined circuit patterns 9 and via holes 11 filled with conductive ink are formed, and then laminated on both surfaces of the central layer 1.
FIGS. 2a to 2d sequentially show a process of fabricating a PCB including embedded chips, according to a second conventional technique, which is disclosed in Japanese Patent Laid-open Publication No. 2004-7006.
In FIG. 2a, a circuit layer 20 having a predetermined circuit pattern 22 and through holes 21 is formed.
In FIG. 2b, an electrical component 23 is mounted on the predetermined circuit pattern 22 of the circuit layer 20.
In FIG. 2c, a hollow portion of a central layer 25 is formed, after which the central layer 25 is processed to have a predetermined circuit pattern 26 and through holes 27 and is then laminated on the circuit layer 20.
In FIG. 2d, a circuit layer 28 having a predetermined circuit pattern 29 and through holes 30 is formed and laminated on the central layer 25.
In such cases, the first and second conventional techniques are disadvantageous because the space between the electrical component and the insulating layer as the central layer is large, and thus, the resultant product has a large size.
Further, the first and second conventional techniques are disadvantageous because the space between the chip and the copper foil layer is large, and thus, efficient radiating effects cannot be obtained.
Furthermore, the second conventional technique is disadvantageous because a build-up process used for lamination takes a long time.
Turning now to FIG. 3a, constitutive layers of a PCB including embedded chips upon lamination are schematically shown, according to a third conventional technique. Also, FIGS. 3b to 3f sequentially show a process of forming a core of each layer of FIG. 3a. The above technique is disclosed in Japanese Patent Laid-open Publication No. 2004-153084.
In FIG. 3a, a lower circuit layer is composed of a film 8 having a predetermined circuit pattern 3 and a radiating pattern 6, in which conductive ink 9 is applied on the radiating pattern 6.
Then, a hollow portion is formed through a film 8 and then the film 8 is further processed to have a predetermined circuit pattern 3 and through holes filled with conductive ink 9, to obtain a central layer. As such, the film 8 is provided in the number of layers corresponding to the thickness of an electrical component 5 to be inserted into the hollow portion thereof.
Finally, an upper circuit layer is formed by processing a film 8 to have a predetermined circuit pattern 3 and through holes filled with conductive ink 9, and then the upper and lower circuit layers are laminated on the central layer having an inserted electrical component 5 at one time.
In FIG. 3b, to form a core of each layer, a copper foil layer 10 is laminated on a film 8.
In FIG. 3c, the copper foil layer 10 on the film 8 is subjected to a general circuit forming process to form a circuit pattern 3. A protective film 11 is applied on a lower surface of the film 8.
In FIG. 3d, through holes 8a are formed at positions corresponding to the upper circuit pattern 3 on the film 8 and the protective film 11.
In FIG. 3e, the through holes 8a are filled with conductive ink 9.
In FIG. 3f, the protective film 11 is removed from the film 8.
However, the third conventional technique is disadvantageous in that because the through holes filled with conductive ink adhere to the chip upon simultaneous lamination, the alignment of the layers cannot be accurately controlled.
Moreover, since the radiation takes place using the radiating pattern, limitations are imposed on fabricating a high density circuit due to the formation of a passage required for emission of the radiating pattern.